In the DFT timing analysis, scan chain design of any SOC or an IC VLSI Chip, lockup latches, and lockup registers play a very important role. Especially these are used in fixing hold timing closure as well as to avoid timing clock skew difficulties. Let us understand these from the timing perspective and their significance in congestion. And we will discuss the difference between both lockup registers and lockup latches. Introduction In the current generation of VLSI technology, SOC’s are made of multi-clock domains with various functional sources. To avoid a large, uncommon path between the clocks of two flip flops from the timing perspective these latches can be the best solution. But the disadvantage of these lockup latches is that they can cause