Power Calculation and Planning in Physical Design of a VLSI chip VLSI Design by VLSI Universe - June 2, 2021July 21, 20210 Power calculation and planning before any signal routing in the VLSI chip physical design is very important. As Power supply rails carry large transient currents which may distort the signal lines using electrostatic discharge if design rules are not met correctly. Introduction to power planning A VLSI chip in the semiconductor industry is intended to perform a specific operation and has to communicate with the outside world through various signals. To have this signal flow to the chip and out of the chip we need a power supply. Hence proper power planning became an essential part of the planning process in the back-end of the VLSI chip design. An appropriate power supply network must be constructed by considering many aspects such as design
Dynamic Power dissipation in CMOS CMOS by VLSI Universe - May 4, 2020July 21, 20210 The CMOS dynamic power is the power dissipated when the logic gate is in the active state. It is mainly due to the switching activity of the i/p signal or mainly due to the charging and discharging of internal node capacitances. Pdynamic = ∝ * CL * (Vdd)^2 * f The CMOS dynamic power (Pdynamic) dissipation is mainly due to The charging and discharging of the load capacitances as the gate switches from one logic to another logic. The short circuit current or leakage current while both PMOS and NMOS stacks are partially ON when not necessary. Activity Factor (∝) The clock gating techniques It will disable the clock to the IDLE portions of the design and hence reducing the power dissipation because of the
